This invention relates, in general, to probe cards for testing unencapsulated integrated circuits (ICs) and, more specifically, to a probe card manufactured from semiconductor materials.
Electrical probing or testing is an important step in the production of semiconductor devices such as monolithic ICs. The probing step constitutes a final inspection step in the production of a wafer before assembling the IC and thus plays an extremely important role in the sense that it gives great influence over the labor saving and work efficiency in subsequent assembly steps. The accuracy or precision of the inspection in the probing step has become a decisive factor for the yield of final products.
A fixed probe board, or probe card, is ordinarily used in the probing step. A typical fixed probe board is disclosed in U.S. Pat. No. 4,563,640 issued to Hasegawa. A fixed probe board comprises a multiplicity of probe needles fixed by a support base and an adhesive layer in an array which matches an array of electrode pads on an integrated circuit to be tested.
A large portion of the cost of manufacturing an integrated circuit is incurred in packaging the integrated circuit. It is desirable to package only functional integrated circuits so that packaging cost is not incurred on devices which will be thrown away. Due to close spacing of electrode pads which are formed on the semiconductor integrated circuits, however, it has been difficult to make contact to enough integrated circuits to make parallel testing practical. The probe needles must be aligned to the pattern of the electrode pads on the integrated circuit and must remain aligned through many test cycles. This alignment problem becomes more difficult as more probe needles are added to the probe card. This problem has made it virtually impossible to test more than four integrated circuits in parallel in chip or wafer form.
In addition to the alignment problem with probe needles, non-planarity in semiconductor wafers created difficult in contacting all of the contact pads. As attempts were made to place more needles in contact with the wafer, this co-planarity problem becomes more acute. Although probe cards have been made with probe needles which can test up to four semiconductor memories in parallel, due to the difficulty set out above operating speed is low, maintenance cost is high and reliability is compromised.
Access time is a figure of merit for semiconductor memories and other high speed devices. Memories must be tested with high speed and sorted into groups having similar access times. Conventional probe needle testing does not allow this high speed testing, and so the sorting operation could only be done after the devices were encapsulated in plastic. This made it difficult to predict availability of memory of a particular access time group until the very end of the assembly process. It is advantageous to know the access time of a memory as early as possible, preferably when the memories are still in wafer form.
Recently, membrane probe card technology has been used to probe integrated circuit chips with closely spaced contact pads. This technology was described by B. Leslie and F. Matta in "Membrane Probe Card Technology (The Future for High Performance Wafer Test)," presented at the 1988 IEEE International Test Conference. This technology has been used to replace probe needles with probe bumps which are formed on a flexible membrane. However, since chips were still tested individually, little improvement was realized in process cycle time.
It has long been known that most integrated circuits are subject to a certain infant mortality level caused by latent defects in the devices. In particular, semiconductor memories which have a relatively large die size and use particularly thin gate oxides, are susceptible to infant mortality problems. The bulk of these early failures can be gleaned out by extensively exercising the circuits at high temperature. Exercising the circuit means to apply power to the circuit, and to send data signals to the circuit which activate various portions of the circuit. A memory circuit which comprises thousands or millions of memory cells, for example, is exercised by addressing each memory cell and storing and retrieving data from that cell. When this process is performed at high temperature, it is called burn-in.
Typically, memory circuits are burned-in for 72 or more hours at temperatures exceeding 100.degree. C. In the past, this process has been performed after the circuits have been assembled and tested. The burn-in process requires that the semiconductor packages be loaded into board of 50 or more units so that they can be exercised in parallel. The boards are then loaded into ovens which control the ambient temperature during burn-in.
Increasingly stringent reliability requirements for semiconductor memories have led many manufacturers to burn-in 100% of their product before shipment. The physical space required to house burn-in ovens for a single manufacturer is enormous. The burn-in of memory circuits along for a single manufacturer may occupy several city blocks of multi-story buildings. Not only physical space is lost: the power required to heat the burn-in ovens and power the exercising circuits is considerable. This is because integrated circuits from a single wafer once encapsulated, loaded into boards, and loaded into an oven, will take up several cubic feet of space which must then be heated and cooled to perform the burn-in.
Not only is physical cost high, but labor cost is high also. Loading packaged integrated circuits into boards and removing them from boards is a labor intensive and is usually a manual operation. Additionally, after burn-in, integrated circuits must be repackaged in shipping tubes or boxes so they can be further processed or sold. These labor intensive operations can add days to the cycle time of a burn-in operation. Attempts to automate board loading and packaging processes have been met with little success, due to the delicate nature of the process.
Although the burn-in operation is designed to improve the reliability of the integrated circuits, oftentimes it compromises the quality of packaged devices. Manual loading and unloading of integrated circuits often damages leads which extend outside the integrated circuit package. This damage is usually not repairable and results in completely functional devices being rejected for physical quality problems. In addition to lead damage, package damage can occur. Also, handling of packaged integrated circuits increases the chances of damage to the circuits themselves by electrostatic discharge. Although burn-in is necessary to provide the desired reliability, the above mentioned quality limitations have long been a costly problem for circuit manufacturers.
One apparatus for burning-in integrated circuits in wafer form is disclosed in U.S. Pat. No. 4,968,931 entitled "Means and Method for Burning-In Integrated Circuit Wafers" and assigned to the assignee of the present invention. This method uses membrane probe card technology described hereinbefore to contact a plurality of integrated circuits in parallel. One difficulty with this method is that due to differential coefficients and thermal expansion between the integrated circuit wafer and the membrane probe card, the probe card had to be designed for operation at a specific temperature and could only be aligned to and contact the integrated circuit wafer once that temperature was reached. This required a relatively elaborate and difficult alignment process, particularly when a large number of integrated circuits having a large number of electrode pads were used.
Conventionally, integrated circuits were formed having an array of electrode pads around the periphery of the IC chip. Recently, however, manufacturers are designing ICs having an array of electrode pads spread across the surface area of the IC chip. For large numbers of electrode pads, conventional probe card technology can not be used to test ICs with such an electrode array. Some manufacturers have resorted to flip chip bonding the integrated circuit onto a test circuit board, testing the ICs, then removing the integrated circuits and repairing the damaged bonds. This relatively expensive process results in significant amounts of damage to the integrated circuits. It would be advantageous to have a probe card technology which could couple to integrated circuits having electrode pads in any configuration quickly, reliably, and without damage to the integrated circuits.